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FUJITSU SEMICONDUCTOR DATA SHEET
DS04-21361-3E
ASSP
Dual Serial Input PLL Frequency Synthesizer
MB15F07SL
s DESCRIPTION
The Fujitsu MB15F07SL is a serial input Phase Locked Loop (PLL) frequency synthesizer with two 1100 MHz prescalers. The two 1100 MHz prescalers have a dual modulus division ratio of 128/129 or 64/65 enabling pulse swallowing operation. The supply voltage range is between 2.4 V and 3.6 V. The MB15F07SL uses the latest BiCMOS process. As a result, the supply current is typically 5 mA at 2.7 V. A refined charge pump supplies a well-balanced output current of 1.5 mA or 6 mA. The charge pump current is selectable by serial data. MB15F07SL is ideally suited for wireless mobile communications, such as GSM and PDC.
s FEATURES
* High frequency operation: PLL 1, 2: 1100 MHz max * Low power supply voltage: VCC = 2.4 to 3.6 V * Ultra Low power supply current: ICC = 5.0 mA typ. (VCC = 2.7 V, Ta = +25C, in PLL1, 2 locking state) ICC = 5.5 mA typ. (VCC = 3.0 V, Ta = +25C, in PLL1, 2 locking state) * Direct power saving function: Power supply current in power saving mode Typ. 0.1 A (VCC = 3.0 V, Ta = +25C), Max. 10 A (VCC = 3.0 V) * Dual modulus prescaler: 1100 MHz prescaler (64/65, 128/129) * Serial input 14-bit programmable reference divider: R = 3 to 16,383 * Serial input programmable divider consisting of: - Binary 7-bit swallow counter: 0 to 127 - Binary 11-bit programmable counter: 3 to 2,047 * Software selectable charge pump current * On-chip phase control for phase comparator * Operating temperature: Ta = -40 to +85C
s PACKAGES
16-pin plastic SSOP 16-pad plastic BCC
(FPT-16P-M05)
(LCC-16P-M04)
MB15F07SL
s PIN ASSIGNMENTS
16-pin SSOP
16-pad BCC
GND2 OSCIN GND1 fin1 VCC1 LD/fout PS1 DO1
1 2 3 4 5 6 7 8 TOP VIEW
16 15 14 13 12 11 10 9
Clock Data LE fin2 VCC2 Xfin2 PS2 DO2 OSCIN GND1 fin1 VCC1 LD/fout PS1 1 2 3 4 5 6
GND2 Clock 16 15 14 13 TOP VIEW 12 11 10 7 8 9 Data LE fin2 VCC2 Xfin2 PS2
DO1 DO2
(FPT-16P-M05)
(LCC-16P-M04)
2
MB15F07SL
s PIN DESCRIPTIONS
Pin no. SSOP-16 BCC-16 1 2 3 4 5 16 1 2 3 4 Pin name GND2 OSCIN GND1 fin1 VCC1 I/O - I - I - Ground for PLL 2 section. The programmable reference divider input. TCXO should be connected with a AC coupling capacitor. Ground for the PLL 1 section. Prescaler input pin for the PLL 1. Connection to an external VCO should be via AC coupling. Power supply voltage input pin for the PLL 1 section. Lock detect signal output (LD)/phase comparator monitoring output (fout). The output signal is selected by LDS bit in a serial data. LDS bit = "H" ; outputs fout signal LDS bit = "L" ; outputs LD signal Power saving mode control for the PLL 1 section. This pin must be set at "L" during Power-ON. (Open is prohibited.) PS1 = "H" ; Normal mode PS1 = "L" ; Power saving mode Charge pump output for the PLL 1 section. Phase characteristics of the phase detector can be selected via programming of the FC-bit. Charge pump output for the PLL 2 section. Phase characteristics of the phase detector can be selected via programming of the FC-bit. Power saving mode control for the PLL 2 section. This pin must be set at "L" during Power-ON. (Open is prohibited.) PS2 = "H" ; Normal mode PS2 = "L" ; Power saving mode Prescaler complementary input for the PLL 2 section. This pin should be grounded via a capacitor. Power supply voltage input pin for the PLL 2 section, the shift register and the oscillator input buffer. When power is OFF, latched data of PLL 2 is lost. Prescaler input pin for the PLL 2. Connection to an external VCO should be via AC coupling. Load enable signal inpunt (with a schmitt trigger input buffer.) When the LE bit is set "H", data in the shift register is transferred to the corresponding latch according to the control bit in the serial data. Serial data input (with a schmitt trigger input buffer.) Data is transferred to the corresponding latch (PLL 1-ref counter, PLL 1prog. counter, PLL 2-ref. counter, PLL 2-prog. counter) according to the control bit in the serial data. Clock input for the 23-bit shift register (with a schmitt trigger input buffer.) One bit of data is shifted into the shift register on a rising edge of the clock. Descriptions
6
5
LD/fout
O
7
6
PS1
I
8
7
Do1
O
9
8
Do2
O
10
9
PS2
I
11 12 13 14
10 11 12 13
Xfin2 VCC2 fin2 LE
I - I I
15
14
Data
I
16
15
Clock
I
3
MB15F07SL
s BLOCK DIAGRAM
VCC1 GND1 5 (4) 3 (2)
PS1 7 (6)
Intermittent mode control (PLL 1)
3-bit latch
LDS SW1 FC1
7-bit latch
Binary 7-bit swallow counter (PLL 1)
11-bit latch
Binary 11-bit programmable counter (PLL 1)
fp1
Phase comp. (PLL 1)
Charge Current pump Switch (PLL 1)
8 Do1 (7)
fin1 4 (3)
Prescaler (PLL 1) 64/65, 128/129
Lock Det. (PLL 1)
2-bit latch
14-bit latch
Binary 14-bit programmable ref. counter (PLL 1)
1-bit latch
C/P setting current CP
LD1
T1
T2
fr1 OSCIN 2 (1) fr2 OR T1 T2
Binary 14-bit programmable ref. counter (PLL 2) C/P setting current CP
AND
Selector
2-bit latch
14-bit latch
1-bit latch
LD fr1 fr2 fp1 fp2 Lock Det. (PLL 2)
6 LD/ (5) fout
(12) fin2 13 Xfin2 11 (10)
Prescaler (PLL 2) 64/65, 128/129
PS2 10 (9)
Intermittent mode control (PLL 2)
LDS SW2 FC2
Binary 7-bit swallow counter (PLL 2)
Binary 11-bit programmable counter (PLL 2)
Phase comp. (PLL 2) fp2
Charge Current pump switch
(PLL 2)
9 Do2 (8)
3-bit latch
7-bit latch
11-bit latch
LE 14 (13) (14) Data 15 Clock 16 (15)
Schmitt circuit
Latch selector
Schmitt circuit Schmitt circuit
CC NN 12
23-bit shift register
12 (11) 1 (16) VCC2 GND2
O : SSOP ( ) : BCC 4
MB15F07SL
s ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage Input voltage Output voltage Storage temperature Symbol VCC VI VO Tstg Rating Min. -0.5 -0.5 GND -55 Max. +4.0 VCC +0.5 VCC +125 Unit V V V C Remark
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage Input voltage Operating temperature Symbol VCC VI Ta Value Min. 2.4 GND -40 Typ. 3.0 - - Max. 3.6 VCC +85 Unit V V C Remark
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
5
MB15F07SL
s ELECTRICAL CHARACTERISTICS
(VCC = 2.4 V to 3.6 V, Ta = -40 to +85C) Parameter Symbol Condition PLL 1, PLL 2 total, fin1 = fin2 = 1100 MHz, VCC1 = VCC2 = 2.7 V (VCC1 = VCC2 = 3.0 V) PS1 = PS2 = "L" PLL 1 PLL 2 - PLL 1, 50 system PLL 2, 50 system - Schmitt trigger input Schmitt trigger input - - - - - - VCC = 3.0 V, IOH = -1 mA VCC = 3.0 V, IOL = 1 mA VCC = 3.0 V, IDOH = -0.5 mA VCC = 3.0 V, IDOL = 0.5 mA VCC = 3.0 V, VOFF = 0.5 V to VCC - 0.5 V VCC = 3.0 V VCC = 3.0 V Value Min. - - 100 100 3 -15* 0.5 VCC x 0.7 + 0.4 - VCC x 0.7 - -1.0 -1.0 0 -100 VCC - 0.4 - VCC - 0.4 - - - 1.0 - - - - - - - - - - - - - - -
8
Typ. 5.0 (5.5) 0.1*2 - - - - -
Max. - 10 1100 1100 40 +2 +2 VCC - VCC x 0.3 - 0.4 - VCC x 0.3 +1.0 +1.0 +100 0 -
Unit
Power supply current* Power saving current
1
ICC
*1
mA A MHz MHz MHz dBm dBm Vp-p
IPS fin1*3 fin1 fin2 fosc Pfin1 Pfin2 VOSC VIH VIL VIH VIL IIH*4 IIL*4 IIH IIL
*4
Operating frequency
fin2
*3
OSCIN fin1 Input sensitivity fin2 OSCIN "H" level input voltage "L" level input voltage "H" level input voltage "L" level input voltage "H" level input current "L" level input current "H" level input current "L" level input current "H" level output voltage "L" level output voltage "H" level output voltage "L" level output voltage High impedance cutoff current "H" level output current "L" level output current Data, Clock, LE PS1, PS2 Data, Clock, LE, PS1, PS2 OSCIN
-15*8
V
V
A
A
VOH LD/fout VOL VDOH VDOL IOFF IOH*4 IOL
*4
V 0.4 - V 0.4 2.5 -1.0 - nA
Do1 Do2 Do1 Do2 LD/fout
mA
(Continued)
6
MB15F07SL
(Continued)
(VCC = 2.4 to 3.6 V, Ta = -40 to +85C) Parameter Symbol Condition CS bit = "H" VCC = 3.0 V, VDOH = VCC/2, CS bit = "L" Ta = +25C VCC = 3.0 V, VDOL= VCC/2, Ta = +25C VDO = VCC/2 0.5 V VDO VCC - 0.5 V -40C Ta +85C, VDO = VCC/2 CS bit = "H" CS bit = "L" Value Min. - - - - - - - Typ. -6.0 -1.5 6.0 1.5 3 10 10 Max. - - - - - - - % % % mA Unit
"H" level output current Do1 Do2 "L" level output current IDOL/IDOH Charge pump current rate *1: *2: *3: *4: *5: *6: *7: *8: vs VDO vs Ta
IDOH*4
IDOL IDOMT*5 IDOVD*6 IDOTA*7
Conditions; fosc = 12 MHz, Ta = +25C, in locking state. VCC1 = VCC2 = 3.0 V, fosc = 12.8 MHz, Ta = +25C, in power saving mode. AC coupling. 1000pF capacitor is connected under the condition of min. operating frequency. The symbol "-" (minus) means direction of current flow. VCC = 3.0 V, Ta = +25C (|I3| - |I4|)/[(|I3| + |I4|)/2] x 100(%) VCC = 3.0 V, Ta = +25C [(|I2| - |I1|)/2]/[(|I1| + |I2|)/2] x 100(%) (Applied to each IDOL, IDOH) VCC = 3.0 V, [|IDO(+85C) - IDO(-40C)|/2]/[|IDO(+85C) + IDO(-40C)|/2] x 100(%) (Applied to each IDOL, IDOH) Prescaler divided ratio Charge pump current Vfin1(min) 64/65 1.5 mA mode -10 dBm fin1 6.0 mA mode -10 dBm 128/129 1.5 mA mode -15 dBm 6.0 mA mode -15 dBm Prescaler divided ratio Charge pump current Vfin2(min) fin2 64/65 1.5 mA mode -15 dBm 6.0 mA mode -10 dBm 128/129 1.5 mA mode -15 dBm 6.0 mA mode -15 dBm
I1 IDOL
I3 I2
IDOH
I2
I4 I1 0.5 Vcc/2 Vcc - 0.5 Vcc
Charge Pump Output Voltage (V)
7
MB15F07SL
s FUNCTIONAL DESCRIPTION
The divide ratio can be calculated using the following equation: fVCO = {(M x N) + A} x fOSC / R (A < N) fVCO : Output frequency of external voltage controlled oscillator (VCO) M: Preset divide ratio of dual modulus prescaler (64 or 128 for PLL 1/PLL 2) N: Preset divide ratio of binary 11-bit programmable counter (3 to 2,047) A: Preset divide ratio of binary 7-bit swallow counter (0 A 127) fOSC : Reference oscillation frequency R: Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
Serial Data Input
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of PLL 1/PLL 2 sections, programmable reference dividers of PLL 1/PLL 2 sections are controlled individually. Serial data of binary data is entered through Data pin. On rising edge of Clock, one bit of serial data is transferred into the shift register. When the LE signal is taken high, the data stored in the shift register is transferred to one of latch of them depending upon the control bit data setting.
Table 1. Control Bit
Control bit CN1 L H L H CN2 L L H H Destination of serial data The programmable reference counter for the PLL 1 The programmable reference counter for the PLL 2 The programmable counter and the swallow counter for the PLL 1 The programmable counter and the swallow counter for the PLL 2
Shift Register Configuration
Programmable Reference Counter
LSB Data Flow MSB
1 C N 1
2 C N 2
3 T 1
4 T 2
5 R 1
6 R 2
7 R 3
8 R 4
9 R 5
10 11 12 13 14 15 16 17 18 19 20 21 22 23 R 6 R 7 R 8 R 9 RRRRR 10 11 12 13 14 C S
X
X
X
X
CN1, CN2 R1 to R14 T1, T2 CS X
: Control bit [Table 1] : Divide ratio setting bits for the programmable reference counter (3 to 16,383)[Table 2] : Test purpose bit [Table 3] : Charge pump currnet select bit [Table 9] : Dummy bits (Set "0" or "1")
NOTE: Data input with MSB first.
8
MB15F07SL
Programmable Counter
LSB MSB Data Flow
1 C N 1
2 C N 2
3 L D S
4 S W
1/2
5 F C
1/2
6 A 1
7 A 2
8 A 3
9 A 4
10 A 5
11 A 6
12 A 7
13 N 1
14 N 2
15 N 3
16 N 4
17 N 5
18 N 6
19 N 7
20 N 8
21 N 9
22 N 10
23 N 11
CN1, CN2: Control bit N1 to N11: Divide ratio setting bits for the programmable counter (3 to 2,047) A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127) SW1/SW2 : Divide ratio setting bit for the prescaler (PLL 1 for the SW1, PLL 2 for the SW2) FC1/FC2 : Phase control bit for the phase detector (PLL 1: FC1, PLL 2: FC2) LDS : LD/fout signal select bit NOTE: Data input with MSB first.
[Table 1] [Table 4] [Table 5] [Table 6] [Table 7] [Table 8]
Table 2. Binary 14-bit Programmable Reference Counter Data Setting
Divide ratio (R) 3 4 16383 R14 0 0 1 R13 0 0 1 R12 0 0 1 R11 0 0 1 R10 0 0 1 R9 0 0 1 R8 0 0 1 R7 0 0 1 R6 0 0 1 R5 0 0 1 R4 0 0 1 R3 0 1 1 R2 1 0 1 R1 1 0 1
Note: Divide ratio less than 3 is prohibited.
Table 3. Test Purpose Bit Setting
T1 L H L H T2 L L H H LD/fout pin state Outputs fr1. Outputs fr2. Outputs fp1. Outputs fp2.
9
MB15F07SL
Table 4. Binary 11-bit Programmable Counter Data Setting
Divide ratio (N) 3 4 2047 N11 0 0 1 N10 0 0 1 N9 0 0 1 N8 0 0 1 N7 0 0 1 N6 0 0 1 N5 0 0 1 N4 0 0 1 N3 0 1 1 N2 1 0 1 N1 1 0 1
Note: Divide ratio less than 3 is prohibited.
Table 5. Binary 7-bit Swallow Counter Data Setting
Divide ratio (N) 0 1 127 A7 0 0 1 A6 0 0 1 A5 0 0 1 A4 0 0 1 A3 0 0 1 A2 0 0 1 A1 0 1 1
Note: Divide ratio (A) range = 0 to 127
Table 6. Prescaler Data Setting
SW = "H" Prescaler divide ratio PLL 1 PLL 2 64/65 64/65 SW = "L" 128/129 128/129
Table 7. Phase Comparator Phase Switching Data Setting
FC1, FC2 = "H" fr > fp fr = fp fr < fp VCO polarity H Z L (1) FC1, FC2 = "L"
(1)
Do1, Do2 L Z H (2)
(2)
VCO Output Frequency
Note: * Z = High-impedance * Depending upon the VCO and LPF polarity, FC bit should be set.
LPF Output Voltage
10
MB15F07SL
Table 8. LD/fout Output Select Data Setting
LDS H L LD signal LD/fout output signal fout (fr1/fr2, fp1/fp2) signals
Table 9. Charge Pump Current Setting
CS H L Current value 6.0 mA 1.5 mA
Power Saving Mode (Intermittent Mode Control Circuit) Table 10. PS Pin Setting
PS pin H L Normal mode Power saving mode Status
The intermittent mode control circuit reduces the PLL power consumption. By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See the Electrical Characteristics chart for the specific value. The phase detector output, Do, becomes high impedance. For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table. Setting the PS pin high, releases the power saving mode, and the device works normally. The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation. When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can cause a major change in the comparator output, resulting in a VCO frequency jump and an increase in lockup time. To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error signal from the phase detector when it returns to normal operation. Notes: *When power (VCC) is first applied, the device must be in standby mode, PS = Low, for at least 1 s. *PS pins must be set at "L" for Power-ON.
OFF tv 1 s ON
VCC
Clock Data LE
,,, ,,,,,,, ,,,,
tps 100 ns (1) (2) (3)
PS
(1) PS = L (power saving mode) at Power-ON (2) Set serial data 1 s later after power supply remains stable (VCC > 2.2 V). (3) Release power saving mode (PS: "L" "H") 100 ns later after setting serial data.
11
MB15F07SL
s SERIAL DATA INPUT TIMING
1st data Control bit Invalid data 2nd data
Data
MSB
LSB
Clock
t1 t7 t2 t3 t6
LE
t4 t5
On rising edge of the clock, one bit of the data is transfered into the shift register. Parameter t1 t2 t3 t4 Min. 20 20 30 30 Typ. - - - - Max. - - - - Unit ns ns ns ns Parameter t5 t6 t7 Min. 100 20 100 Typ. - - - Max. - - - Unit ns ns ns
Note: LE should be "L" when the data is transferred into the shift register.
12
MB15F07SL
s PHASE COMPARATOR OUTPUT WAVEFORM
fr1/ fr2
fp1/ fp2
tWU tWL
LD
(FC bit = High)
DO1/ DO2
(FC bit = Low)
DO1/ DO2
LD Output Logic Table
IF-PLL section Locking state/Power saving state Locking state/Power saving state Unlocking state Unlocking state
RF-PLL section Locking state/Power saving state Unlocking state Locking state/Power saving state Unlocking state
LD output H L L L
Notes: * Phase error detection range = -2 to +2
* * * *
Pulses on Do1/2 signals are output to prevent dead zone. LD output becomes low when phase error is tWU or more. LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more. tWU and tWL depend on OSCIN input frequency as follows. tWU > 2/fosc: i. e. tWU > 156.3 ns when fosc = 12.8 MHz tWU < 4/fosc: i. e. tWL < 312.5 ns when fosc = 12.8 MHz
13
MB15F07SL
s MEASURMENT CIRCUIT (for Measuring Input Sensitivity fin/OSCIN)
fout Oscilloscope VCC1
0.1 F S.G. 50 1000 pF 1000 pF 50
S.G.
DO1 8
PS1 7
LD/fout 6
VCC1 5
fin1 4
GND1 3
OSCIN 2
GND2 1
9 DO2
10 PS2
11 Xfin2
12 VCC2
13 fin2
14 LE
15 Data
16 Clock
S.G.
1000 pF Controller (divide ratio setting) 50 1000 pF VCC2
0.1 F
Note: SSOP-16
14
MB15F07SL
s TYPICAL CHARACTERISTICS
1. fin input sensitivity * fin1 input sensitivity
PLL1 input sensitivity - Input frequency 10 5 0 Pfin1 (dBm) -5 -10 -15 -20 -25 -30 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 fin1 (MHz) Ta = +25 C
,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,
SPEC
VCC = 2.4 V VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V
* fin2 input sensitivity
PLL2 input sensitivity - Input frequency 10 5 0 -5 Pfin2 (dBm) -10 -15 -20 -25 -30 -35 -40 0 100 200 300 400 500 600 700 800 900 fin2 (MHz) Ta = +25 C
,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,
SPEC VCC = 2.4 V VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V 1000 1100 1200 1300 1400 1500
15
MB15F07SL
2. OSCIN input sensitivity * OSCIN
10 0 -10 VOSC (dBm) -20 -30 -40 -50 0 5 10 15 20 25 fOSC (MHz) 30 35 40 VCC = 2.4 V VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V 45 50
Ta = +25 C
,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,
Input sensitivity - Input frequency SPEC
16
MB15F07SL
3. Do output current (PLL1) * 1.5 mA mode
VDO - IDO Ta = +25 C VCC = 3 V
10.00 Change pump output current IDO (mA)
2.000 /div
IDOL
0
IDOH
-10.00 0 .6000/div Change pump output voltage VDO (V) 4.800
* 6.0 mA mode
Ta = +25 C VCC = 3 V IDOL
VDO - IDO
10.00 Change pump output current IDO (mA)
2.000 /div
0
IDOH
-10.00 0 .6000/div Change pump output voltage VDO (V) 4.800
17
MB15F07SL
4. Do output current (PLL2)
* 1.5 mA mode
VDO - IDO Ta = +25 C VCC = 3 V
10.00 Change pump output current IDO (mA)
2.000 /div
IDOL
0 IDOH
-10.00 0 .6000/div Change pump output voltage VDO (V) 4.800
* 6.0 mA mode
VDO - IDO Ta = +25 C VCC = 3 V IDOL
10.00 Change pump output current IDO (mA)
2.000 /div
0
IDOH
-10.00 0 .6000/div Change pump output voltage VDO (V) 4.800
18
MB15F07SL
5. fin input impedance
fin1 input impedance
1 : 360.88 -683.25 100 MHz 2 : 30.641 -206.18 400 MHz 3 : 10.805 -92.172 800 MHz 4 : 10.076 -54.955 1100 MHz
1
2 4 3
START
100.000 000 MHz
STOP 1 100.000 000 MHz
fin2 input impedance
1 : 299.88 -658.06 100 MHz 2: 26.68 -184.5 400 MHz
3 : 11.949 -75.16 800 MHz 1 4 : 14.246 -36.49 1100 MHz
4
2
3 START 100.000 000 MHz STOP 1 100.000 000 MHz
19
MB15F07SL
6. OSCIN input impedance
OSCIN input impedance
1 : 9.451 k -3.1875 k 3 MHz 2 : 4.7255 k -5.1685 k 10 MHz 3 : 1.6918 k -3.8045 k 4 20 MHz 1 3 2 4 : 463.75 -2.1069 k 40 MHz
START 3.000 000 MHz
STOP 40.000 000 MHz
20
MB15F07SL
s REFERENCE INFORMATION
Test Circuit S.G. OSCIN fin Do LPF fVCO = 1005 MHz KV = 20 MHz/V fr = 200 kHz fOSC = 13 MHz LPF VCC = 3.0 V VVCO = 3.3 V Ta = +25 C CP : 6 mA mode 1.1 k
Spectrum Analyzer
1800 pF VCO
2.2 k 0.018 F
330 pF
* PLL Reference Leakage
ATTEN 10 dB RL 0 dBm 10 dB/ MKR -71.16 dB 200 kHz
CENTER 1.005000 GHz RBW 10 kHz VBW 10 kHz
SPAN 1.000 MHz SWP 50.0 ms
* PLL Phase Noise
ATTEN 10 dB RL 0 dBm 10 dB/ MKR -54.83 dB 9.58 kHz
C/N = 79.6 (dBc/Hz)
BW = 16 kHz
CENTER 1.005000 GHz RBW 300 kHz VBW 300 kHz
SPAN 50.00 kHz SWP 1.40 s
(Continued) 21
MB15F07SL
(Continued)
* PLL Lock Up time
* PLL Lock Up time
1005 MH1031 MHz within 1 KHz LchHch 299 s 50.00000 MHz 50.00000 MHz
1031 MH1005 MHz within 1 KHz HchLch 330 s
10.00000 MHz/div
10.00000 MHz/div
0 Hz 0S 30.00500 MHz 2.0000000 ms
10.00000 MHz 0S 30.00500 MHz 2.0000000 ms
2.000 kHz/div
2.000 kHz/div
29.99500 MHz 0S 2.0000000 ms
29.99500 MHz 0S 2.0000000 ms Meas # 91
22
MB15F07SL
s APPLICATION EXAMPLE
OUTPUT
VCO
LPF
1000 pF
3V 0.1 F 1000 pF
from controller
Clock 16
Data 15
LE 14
fin2 13
VCC2 12
Xfin2 11
PS2 10
Do2 9
MB15F07SL
1 GND2
2 OSCIN
3 GND1
4 fin1
5 VCC1
6 LD/fout 3V
7 PS1
8 Do1
1000 pF TCXO
1000 pF 0.1 F
LockDet
OUTPUT
VCO
LPF
Note: SSOP-16
s USAGE PRECAUTIONS
(1) VCC2 must equal Vcc1. Even if either PLL 2 or PLL 1 is not used, power must be supplied to both VCC2 and VCC1 to keep them equal. It is recommended that the non-use PLL is controlled by power saving function. (2) To protect against damage by electrostatic discharge, note the following handling precautions: -Store and transport devices in conductive containers. -Use properly grounded workstations, tools, and equipment. -Turn off power before inserting or removing this device into or from a socket. -Protect leads with conductive sheet, when transporting a board mounted device.
23
MB15F07SL
s ORDERING INFORMATION
Part number MB15F07SLPFV1 MB15F07SLPV1 Package 16-pin plastic SSOP (FPT-16P-M05) 16-pad plastic BCC (LCC-16P-M04) Remarks
24
MB15F07SL
s PACKAGE DIMENSIONS
16-pin plastic SSOP (FPT-16P-M05)
Note 1 ) * : These dimensions do not include resin protrusion. Note 2 ) Pins width and pins thickness include plating thickness.
* 5.000.10(.197.004)
16 9
0.170.03 (.007.001)
* 4.400.10
INDEX
6.400.20 (.173.004) (.252.008)
Details of "A" part 1.25 -0.10 .049 -.004 LEAD No.
1 8
+0.20 +.008
(Mounting height)
0.65(.026)
"A" 0.240.08 (.009.003) 0.13(.005)
M
0~8 0.100.10 (Stand off) (.004.004) 0.25(.010)
0.10(.004)
0.500.20 (.020.008) 0.45/0.75 (.018/.030)
C
1999 FUJITSU LIMITED F16013S-3C-5
Dimensions in mm (inches)
(Continued)
25
MB15F07SL
16-pad plastic BCC (LCC-16P-M04)
4.550.10 (.179.004)
14 9
0.80(.031)MAX Mounting height 0.65(.026) TYP
9
3.40(.134)TYP 0.3250.10 (.013.004)
14
0.80(.031) REF
INDEX AREA
4.200.10 (.165.004)
3.25(.128) TYP "A" "B" 1.55(.061) REF
0.400.10 (.016.004)
1
6
0.0750.025 (.003.001) (Stand off)
6
1.725(.068) REF Details of "B" part 0.600.10 (.024.004)
1
Details of "A" part 0.750.10 (.030.004) 0.05(.002)
0.400.10 (.016.004)
0.600.10 (.024.004)
C
1999 FUJITSU LIMITED C16015S-1C-1
Dimensions in mm (inches)
26
MB15F07SL
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8588, Japan Tel: +81-44-754-3763 Fax: +81-44-754-3329
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
http://www.fujitsu.co.jp/
North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, USA Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://www.fujitsu-fme.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220
http://www.fmap.com.sg/
F0002 (c) FUJITSU LIMITED Printed in Japan

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